An Efficient VLSI Architecture for Fast Fourier Transform Using Reversible Logic Gates

Abstract

Fast Fourier Transform (FFT) has become one of the most essential computational techniques in signal processing, digital communication, and biomedical applications. As devices migrate toward energy-efficient, high-performance systems, the demand for optimized Very Large Scale Integration (VLSI) designs of FFT architectures has increased. Traditional CMOS-based FFT circuits suffer from excessive power consumption, heat dissipation, and scalability issues. Reversible logic, with its ability to eliminate information loss during computation, offers a promising paradigm for designing low-power and high-speed VLSI systems. This paper presents a comprehensive review and analysis of efficient VLSI architecture for FFT using reversible logic gates. The proposed framework focuses on minimizing power dissipation while maintaining high throughput and scalability. It examines reversible logic designs such as Toffoli, Fredkin, and Peres gates for constructing FFT butterfly structures. A comparative analysis with conventional designs highlights reductions in switching activity, transistor count, and energy loss. The paper also reviews recent advances in low-power FFT VLSI architectures and discusses open challenges such as quantum cost, garbage outputs, and synthesis complexity. The findings demonstrate that reversible gate-based FFT architectures can achieve significant improvements in power efficiency and sustainability, paving the way for next-generation low-power VLSI systems.