VLSI Architecture for 5/3 2-D Discrete Wavelet Transform using Multiplier-less and Kogge Stone Adder Technique

Abstract

This paper presents an efficient VLSI architecture for implementing the 5/3 2-D Discrete Wavelet Transform (DWT) using a multiplier-less approach combined with the Kogge-Stone Adder (KSA) technique. The 5/3 DWT is widely used in image processing applications, particularly in lossless compression standards such as JPEG2000, due to its simplicity and high performance. However, conventional implementations rely heavily on multipliers, which increase hardware complexity, power consumption, and delay. To address these challenges, the proposed design eliminates multipliers by employing shift-and-add operations and Distributed Arithmetic (DA), thereby reducing area and improving energy efficiency. The architecture performs 2-D DWT through sequential row-wise and column-wise 1-D transformations using the lifting scheme. Intermediate results are stored in memory elements to facilitate efficient data flow. The integration of the Kogge-Stone Adder, a parallel prefix adder known for its fast carry propagation, significantly enhances the speed of arithmetic operations by minimizing critical path delay. This results in improved throughput and higher operating frequency. A comparative analysis is carried out using key performance metrics such as the number of registers, Look-Up Tables (LUTs), and maximum frequency. The results demonstrate that the proposed design achieves substantial reductions in hardware resources along with a significant increase in speed. Overall, the architecture provides an optimized solution for high-speed, low-power, and area-efficient implementation of 2-D DWT, making it suitable for real-time image processing and embedded system applications.