Energy-Efficient SRAM Design in 7nm and 10nm FinFET Technologies: A Comparative Study of 6T, 7T and 8T Architectures
Keywords:
SRAM, FinFET, 7nm Technology, 10nm Technology, Leakage Power, Power-Delay Product, Low-Power VLSIAbstract
The continuous scaling of semiconductor technology into sub-10nm regimes has intensified the need for energy-efficient and high-performance SRAM architectures. This paper presents a comparative design and performance analysis of 6T, 7T, and 8T SRAM cells implemented using 10nm and 7nm FinFET technologies. The proposed study integrates multi-threshold device configuration and leakage reduction techniques to enhance power efficiency and switching speed. The circuits were designed and validated using DSCH and MICROWIND tools, and key performance parameters including leakage power, static power, dynamic power, propagation delay, and Power-Delay Product (PDP) were extracted. Simulation results demonstrate that FinFET technology significantly reduces leakage and dynamic power compared to conventional CMOS designs. Among the evaluated architectures, the 8T SRAM cell implemented at 7nm FinFET achieves the lowest power dissipation and minimum delay, resulting in superior energy efficiency. The findings confirm that optimized FinFET-based 8T SRAM architectures are highly suitable for low-power, high-speed memory applications in advanced technology nodes.
References
E. Mani, P. Nimmagadda, S. J. Basha et al., “A FinFET-based low-power, stable 8T SRAM cell with high yield,” AEU — International Journal of Electronics and Communications, vol. 159, pp. 155102, 2023.
D. Singh, S. Chaudhary, B. Dewan, and M. Yadav, “Performance investigation of different low power SRAM cell topologies using stacked-channel tri-gate junctionless FinFET,” Microelectronics Journal, vol. 147, pp. 106122, 2024.
E. Abbasian, S. Birla, and M. Gholipour, “Ultra-low-power and stable 10-nm FinFET 10T sub-threshold SRAM,” Microelectronics Journal, vol. 119, pp. 105316, 2022.
A. Dolatshah, E. Abbasian, M. Nayeri, and S. Sofimowloodi, “A sub-threshold 10T FinFET SRAM cell design for low-power applications,” AEÜ — International Journal of Electronics and Communications, vol. 146, pp. 154417, 2022.
E. Abbasian, R. Birla, and B. Ebrahimi, “A low-power SRAM design with enhanced stability and ION/IOFF ratio in FinFET technology for wearable device applications,” International Journal of Electronics, vol. 111, no. 5, pp. 453–466, 2024.
A. Navaneetha and K. Bikshalu, “Reliability and power analysis of FinFET based SRAM,” Arabian Journal for Science and Engineering, vol. 47, pp. 4991–5002, 2022.
S. Ruhil and V. Kumar, “A 7T high stable and low power SRAM cell design using QG-SNS FinFET,” AEU — International Journal of Electronics and Communications, vol. 158, pp. 102178, 2023.
L. B. Shaik and A. K. Singh, “Improved leaky mitigation in an IL7T SRAM cell based on 18 nm FinFET,” International Journal of Electronics, vol. 112, pp. 350–360, 2025.
L. J. B. Shaik and M. R. Rao, “FinFET based SRAM cells design using power gating and leakage control,” International Journal of Circuit Theory and Applications, vol. 52, no. 8, pp. 1837–1847, 2024.
L. J. Zhang, C. Wu, Y. Ma, J. B. Zheng and L. F. Mao, “Leakage power reduction techniques of 55 nm SRAM cells,” IETE Technical Review, vol. 28, no. 2, pp. 135–145, 2011 — frequently cited in recent SRAM optimization work.
A. Sachdeva and V. K. Tomar, “A Schmitt-trigger based low read power 12T SRAM cell,” Analog Integrated Circuits and Signal Processing, vol. 105, no. 2, pp. 275–295, 2020 — foundational design referenced in low-power SRAM studies.
T. Dutta, G. Pahwa, A. R. Trivedi et al., “Performance evaluation of 7-nm node negative capacitance FinFET-based SRAM,” IEEE Electron Device Letters, vol. 38, no. 8, pp. 1161–1164, 2017 — widely used for FinFET SRAM performance benchmarks.
M. U. Mohammed, A. Nizam, L. Ali, and M. H. Chowdhury, “FinFET based SRAMs in Sub-10nm domain,” Microelectronics Journal, vol. 114, Article ID 105116, 2021.
C. Duari, S. Birla, and A. K. Singh, “Dual port 8T SRAM cell using FinFET & CMOS logic for leakage reduction and enhanced read & write stability,” Journal of Integrated Circuits and Systems, vol. 15, no. 2, pp. 1–7, 2020.
S. Sayyah Ensan, M. H. Moaiyeri, B. Ebrahimi, S. Hessabi, and A. Afzali-Kusha, “A low-leakage and high-writable SRAM cell with back-gate biasing in FinFET technology,” Journal of Computational Electronics, vol. 18, no. 2, pp. 519–526, 2019.
M. S. Badran, H. H. Issa, S. M. Eisa, and H. F. Ragai, “Low leakage current symmetrical dual-k 7 nm trigate bulk underlap FinFET for ultra low power applications,” IEEE Access, vol. 7, pp. 17256–17262, 2019.
X. Xue, A. Sai Kumar, O. I. Khalaf et al., “Design and performance analysis of 32×32 memory array SRAM for low-power applications,” Electronics, vol. 12, no. 4, p. 834, 2023.
S. Pal, S. Bose, K. Wing-Hung, and A. Islam, “A highly stable reliable SRAM cell design for low power applications,” Microelectronics Reliability, vol. 105, Article ID 113503, 2020.
Downloads
How to Cite
Issue
Section
License
Copyright (c) 2025 International Journal of Engineering Science & Humanities
This work is licensed under a Creative Commons Attribution 4.0 International License.
